Enhanced Super I/O Controller with Fast IR
Datasheet
Table 19.16 - nDSR2 MUXING
MUX CONTROLS
PIN
NAME
16 BIT ADDRESS
QUAL. (CR24.6)
SERIRQSEL
(LD8:CRC0.2)
SELECTED FUNCTION
nDSR2
0
0
1
1
1
nDSR2 (default)
0
IRQ10
(Note 19.8)
1
SA15
0
Reserved
Note 19.8 LD8:CRB5.7 controls the IRQ10/nSMI interrupt mux.
STATE OF
UNCONNECTED
INPUTS
1
-
0
-
PIN
NAME
nDCD2
Table 19.17 - nDCD2 MUXING
MUX CONTROLS
8042COMSEL.
(LD8:CRC0.3)
SERIRQSEL
(LD8:CRC0.2)
SELECTED FUNCTION
0
1
nDCD2 (default)
0
0
IRQ11
1
1
P12
1
0
Reserved
STATE OF
UNCONNECTED
INPUTS
1
-
-
-
PIN
NAME
nRI2
Table 19.18 - nRI2 MUXING
MUX CONTROLS
8042COMSEL.
(LD8:CRC0.3)
SERIRQSEL
(LD8:CRC0.2)
SELECTED FUNCTION
0
1
nRI2 (default)
0
0
IRQ12
1
1
P16
1
0
Reserved
STATE OF
UNCONNECTED
INPUTS
1
-
-
-
PIN NAME
DRQ3
Table 19.19 - DRQ3 MUXING
MUX CONTROL
DMA3SEL
(LD8:CRC0.1)
1
0
SELECTED FUNCTION
DRQ3 (default)
P12
STATE OF
UNCONNECTED
INPUTS
-
-
SMSC FDC37C672
Page 140
DATASHEET
Rev. 10-29-03