FDC37C672 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
FDC37C672 Datasheet PDF : 173 Pages
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Enhanced Super I/O Controller with Fast IR
Datasheet
NAME
REG INDEX
DEFINITION
SMI Status Register 1 0xB6 R/W This register is used to read the status of the SMI inputs.
STATE
C
Default = 0x00
The following bits must be cleared at their source.
on Vcc POR
Bit[0] Reserved
Bit[1] PINT (Parallel Port Interrupt)
Bit[2] U2INT (UART 2 Interrupt)
Bit[3] U1INT (UART 1 Interrupt)
Bit[4] FINT (Floppy Disk Controller Interrupt)
Bit[5] Reserved
Bit[6] Reserved
Bit[7] WDT (Watch Dog Timer)
SMI Status Register 2 0xB7 R/W This register is used to read the status of the SMI inputs.
C
Bit[0] MINT: Mouse Interrupt. Cleared at source.
Default = 0x00
Bit[1] KINT: Keyboard Interrupt. Cleared at source.
on Vcc POR
Bit[2] IRINT: This bit is set by a transition on the IR pin
(RDX2 or IRRX as selected in CR L5-F1-B6 i.e., after the
MUX). Cleared by a read of this register.
Bit[3] Reserved
Bit[4] P12: 8042 P1.2. Cleared at source
Bit[7:5] Reserved
Default = 0x00
0xB8 R/W Bits[7:0] Reserved
C
on VTR POR
Pin Multiplex Controls
0xC0
Bit[0] IR Mode Select
Bit[1] DMA 3 Select
Default = 0x06 on Vcc
POR
Bit[2] Serial IRQ Select
Bit[3] 8042 Select
Bit[4] IRRX 3 Select
Bit[5:7] Reserved
Force Disk Change
0xC1
Bit[0] Force Change 0
C,R
Default = 0x03 on Vcc
POR
(R/W)
Bit[1] Force Change 1
Bit[7:2] Reserved
Force Change[1:0] can be written to 1 but are not clearable
by software.
Force Change 1 is cleared on nSTEP and nDS1 Force
Change 0 is cleared on nSTEP and nDS0
Floppy Data Rate
Select Shadow
DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND Force
Change 0) OR (nDS1 AND Force Change 1) OR nDSKCHG
0xC2
Bit[0] Data Rate Select 0
C
(R)
Bit[1] Data Rate Select 1
Bit[2] PRECOMP 0
Bit[3] PRECOMP 1
Bit[4] PRECOMP 2
Bit[5] Reserved
Bit[6] Power Down
Bit[7] Soft Reset
SMSC FDC37C672
Page 138
DATASHEET
Rev. 10-29-03
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