Enhanced Super I/O Controller with Fast IR
Datasheet
NAME
UART1 FIFO Control
Shadow
UART2 FIFO Control
Shadow
REG INDEX
0xC3
0xC4
DEFINITION
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
STATE
C
C
PIN
NAME
nRTS2
Table 19.13 - nRTS MUXING
MUX CONTROLS
16 BIT ADDRESS QUAL.
(CR24.6)
SERIRQSEL
(LD8:CRC0.2)
SELECTED FUNCTION
0
1
nRTS2 (default)
0
0
IRQ5
1
1
SA12
1
0
Reserved
STATE OF
UNCONNECTED
INPUTS
-
-
0
-
PIN
NAME
nCTS2
Table 19.14 - nCTS2 MUXING
MUX CONTROLS
16 BIT ADDRESS
QUAL. (CR24.6)
SERIRQSEL
(LD8:CRC0.2)
SELECTED FUNCTION
0
1
nCTS2 (default)
0
0
IRQ6
1
1
SA13
1
0
Reserved
STATE OF
UNCONNECTED
INPUTS
1
-
0
-
PIN
NAME
nDTR2
Table 19.15 - nDTR2 MUXING
MUX CONTROLS
16 BIT ADDRESS
QUAL. (CR24.6)
SERIRQSEL
(LD8:CRC0.2)
SELECTED FUNCTION
0
1
nDTR2 (default)
0
0
IRQ7
1
1
SA14
1
0
Reserved
STATE OF
UNCONNECTED
INPUTS
-
-
0
-
SMSC FDC37C672
Page 139
DATASHEET
Rev. 10-29-03