ISPGDX160V-3Q208I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
ISPGDX160V-3Q208I Datasheet PDF : 36 Pages
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Specifications ispGDX160VA
External Timing Parameters
Over Recommended Operating Conditions
-7
-9
TEST1
UNITS
PARAMETER COND. #
DESCRIPTION
tpd2
A 1 Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX)
tsel2
A 2 Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)
S fmax (Tog.) – 3 Clock Frequency, Max. Toggle
fmax (Ext.)
–
4
Clock Frequency with External Feedback (
1
tsu3+tgco1
)
tsu1
– 5 Input Latch or Register Setup Time Before Yx
E tsu2
– 6 Input Latch or Register Setup Time Before I/O Clock
tsu3
IC tsu4
– 7 Output Latch or Register Setup Time Before Yx
– 8 Output Latch or Register Setup Time Before I/O Clock
D tsuce1
tsuce2
– 9 Global Clock Enable Setup Time Before Yx
– 10 Global Clock Enable Setup Time Before I/O Clock
V tsuce3
E th1
th2
– 11 I/O Clock Enable Setup Time Before Yx
– 12 Input Latch or Reg. Hold Time (Yx)
– 13 Input Latch or Reg. Hold Time (I/O Clock)
E U th3
– 14 Output Latch or Reg. Hold Time (Yx)
th4
– 15 Output Latch or Reg. Hold Time (I/O Clock)
D IN thce1
thce2
– 16 Global Clock Enable Hold Time (Yx)
– 17 Global Clock Enable Hold Time (I/O Clock)
thce3
T tgco12
T tgco22
C tco12
– 18 I/O Clock Enable Hold Time (Yx)
A 19 Output Latch or Reg. Clock (from Yx) to Output Delay
A 20 Input Latch or Register Clock (from Yx) to Output Delay
A 21 Output Latch or Register Clock (from I/O pin) to Output Delay
N tco22
A 22 Input Latch or Register Clock (from I/O pin) to Output Delay
ten2
B 23 Input to Output Enable
E tdis2
C 24 Input to Output Disable
O ttoeen2
B 25 Test OE Output Enable
L ttoedis2
C 26 Test OE Output Disable
E C twh
– 27 Clock Pulse Duration, High
twl
– 28 Clock Pulse Duration, Low
S IS trst
– 29 Register Reset Delay from RESET Low
trw
– 30 Reset Pulse Width
tsl
D 31 Output Delay Adder for Output Timings Using Slow Slew Rate
D tsk
A 32 Output Skew (tgco1 Across Chip)
MIN. MAX. MIN. MAX.
– 7.0 – 9.0 ns
– 7.0 – 9.0 ns
100 – 83 – MHz
80 – 62.5 – MHz
5.5 – 7.0 – ns
4.5 – 6.0 – ns
5.5 – 7.0 – ns
4.5 – 6.0 – ns
3.5 – 4.0 – ns
2.5 – 3.0 – ns
6.5 – 8.5 – ns
0.0 – 0.0 – ns
2.5 – 3.0 – ns
0.0 – 0.0 – ns
2.5 – 3.0 – ns
0.0 – 0.0 – ns
2.5 – 3.0 – ns
0.0 – 0.0 – ns
– 7.0 – 9.0 ns
– 11.0 – 13.5 ns
– 9.0 – 11.5 ns
– 13.0 – 15.7 ns
– 8.5 – 10.5 ns
– 8.5 – 10.5 ns
– 8.5 – 10.5 ns
– 8.5 – 10.5 ns
5.0 – 6.0 – ns
5.0 – 6.0 – ns
– 18.0 – 22.0 ns
14.0 – 18.0 – ns
– 7.0 – 9.0 ns
– 0.5 – 1.0 ns
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
12
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