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ISPGDX160V-3Q208I View Datasheet(PDF) - Lattice Semiconductor

Part Name
Description
Manufacturer
ISPGDX160V-3Q208I
Lattice
Lattice Semiconductor 
ISPGDX160V-3Q208I Datasheet PDF : 36 Pages
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Specifications ispGDX160V
Switching Test Conditions
Input Pulse Levels
GND to 3.0V
+ 3.3V
Input Rise and Fall Time
1.5ns 10% to 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
See figure at right
S 3-state levels are measured 0.5V from steady-state
active level.
Device
Output
R1
Test
Point
R2
CL*
E Output Load Conditions
TEST CONDITION
IC A
Active High
D B
Active Low
Active High to Z
V E C
at VOH -0.5V
Active Low to Z
at VOL+0.5V
E U D Slow Slew
R1
153
153
R2
134
134
134
CL
35pF
35pF
35pF
5pF
153
5pF
35pF
Table 2-0004A
*CL includes Test Fixture and Probe Capacitance.
DC Electrical Characteristics
D IN Over Recommended Operating Conditions
SYMBOL
PARAMETER
T VOL Output Low Voltage
T VOH Output High Voltage
IIL
Input or I/O Low Leakage Current
C N IIH
Input or I/O High Leakage Current
IIL-PU
E IBHLS
O IBHHS
L IBHLO
E C IBHHO
IBHT
IOS1
S IS ICCQ4
I/O Active Pull-Up Current
Bus Hold Low Sustaining Current
Bus Hold High Sustaining Current
Bus Hold Low Overdrive Current
Bus Hold High Overdrive Current
Bus Hold Trip Points
Output Short Circuit Current
Quiescent Power Supply Current
ICC
Dynamic Power Supply Current
per Input Switching
D ICONT5 Maximum Continuous I/O Pin Sink
CONDITION
IOL =24 mA
IOH =-12 mA
0V VIN VIL (Max.)
VCC VIN 5.25V
0V VIN VIL
VIN = VIL (Max.)
VIN = VIH (Min.)
0V VIN VCC
0V VIN VCC
VCC = 3.3V, VOUT = 0.5V, TA = 25˚C
VIL = 0.5V, VIH = VCC
One input toggling @ 50% duty cycle,
outputs open.
MIN.
2.4
50
-50
VIL
TYP.2
70
See
Note 3
MAX.
0.55
-10
10
-150
550
-550
VIH
-250
UNITS
V
V
µA
µA
µA
µA
µA
µA
µA
V
mA
mA
mA/MHz
96
mA
Current Through Any GND Pin
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2. Typical values are at VCC = 3.3V and TA = 25oC.
3. I / MHz = (0.01 x I/O cell fanout) + 0.04
CC
e.g. An input driving four I/O cells at 40 MHz results in a dynamic ICC of approximately ((0.01 x 4) + 0.04) x 40 = 3.2 mA.
4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bidirectionals.
5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin.
17

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