ISPGDX160V-3Q208I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
ISPGDX160V-3Q208I Datasheet PDF : 36 Pages
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Specifications ispGDX160V
External Timing Parameters (Continued)
ispGDX160V timings are specified with a GRP load apply to any signal path traversing the GRP (MUXA-D,
(fanout) of four I/O cells. The figure below shows the ∆ OE, CLK/CLKEN, MUXsel0-1). Global Clock signals
GRP Delay with increased GRP loads. These deltas which do not use the GRP have no fanout delay adder.
ispGDX160V Maximum ∆ GRP Delay vs. I/O Cell Fanout
1.6
S 1.4
1.2
E 1.0
0.8
IC 0.6
D 0.4
0.2
V E 0.0
0 4 10 20 30 40 50 60 70
SELDEICSTCODNETINU I/OCellFanout
19
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