ISPGDX160V-3Q208I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
ISPGDX160V-3Q208I Datasheet PDF : 36 Pages
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Specifications ispGDX160VA
Internal Timing Parameters1
Over Recommended Operating Conditions
-7
-9
PARAMETER #
DESCRIPTION1
MIN. MAX. MIN. MAX. UNITS
Inputs
tio
GRP
S tgrp
MUX
tmuxd
E tmuxexp
tmuxs
IC tmuxsio
tmuxsg
D tmuxselexp
Register
V E tiolat
tiosu
E tioh
U tioco
tior
D tcesu
IN tceh
Data Path
tfdbk
T T tiobp
tioob
C tmuxcg
N tmuxcio
tiodg
E tiodio
O Outputs
L tob
E C tobs
toeen
toedis
S IS tgoe
ttoe
Clocks
D tioclk
32 Input Buffer Delay
33 GRP Delay
34 I/O Cell MUX A/B/C/D Data Delay
35 I/O Cell MUX A/B/C/D Expander Delay
36 I/O Cell Data Select
37 I/O Cell Data Select (I/O Clock)
38 I/O Cell Data Select (Yx Clock)
39 I/O Cell MUX Data Select Expander Delay
40 I/O Latch Delay
41 I/O Register Setup Time Before Clock
42 I/O Register Hold Time After Clock
43 I/O Register Clock to Output Delay
44 I/O Reset to Output Delay
45 I/O Clock Enable Setup Time Before Clock
46 I/O Clock Enable Hold Time After Clock
47 I/O Register Feedback Delay
48 I/O Register Bypass Delay
49 I/O Register Output Buffer Delay
50 I/O Register A/B/C/D Data Input MUX Delay (Yx Clock)
51 I/O Register A/B/C/D Data Input MUX Delay (I/O Clock)
52 I/O Register I/O MUX Delay (Yx Clock)
53 I/O Register I/O MUX Delay (I/O Clock)
54 Output Buffer Delay
55 Output Buffer Delay (Slow Slew Option)
56 I/O Cell OE to Output Enable
57 I/O Cell OE to Output Disable
58 GRP Output Enable and Disable Delay
59 Test OE Enable and Disable Delay
60 I/O Clock Delay
— 1.4 — 1.9 ns
— 1.1 — 1.1 ns
— 2.0 — 2.5 ns
— 2.5 — 3.0 ns
— 2.0 — 2.5 ns
— 4.5 — 6.0 ns
— 2.5 — 3.0 ns
— 2.5 — 3.0 ns
— 1.0 — 1.0 ns
— 3.2 — 4.4 ns
— 2.3 — 2.6 ns
— 0.5 — 0.5 ns
— 1.5 — 1.5 ns
— 2.5 — 2.0 ns
— 1.0 — 2.0 ns
— 1.2 — 1.3 ns
— 0.3 — 0.6 ns
— 0.6 — 0.7 ns
— 2.5 — 3.0 ns
— 4.5 — 6.0 ns
— 5.0 — 6.0 ns
— 7.0 — 9.0 ns
— 2.2 — 2.9 ns
— 9.2 — 11.9 ns
— 6.0 — 7.5 ns
— 6.0 — 7.5 ns
— 0.0 — 0.0 ns
— 2.5 — 3.0 ns
— 3.2 — 4.4 ns
tgclk
61 Global Clock Delay
— 2.7 — 3.4 ns
tgclkeng
62 Global Clock Enable (Yx Clock)
— 3.7 — 5.4 ns
tgclkenio
63 Global Clock Enable (I/O Clock)
— 5.7 — 8.4 ns
tioclkeng
64 I/O Clock Enable (Yx Clock)
— 4.2 — 6.4 ns
Global Reset
tgr
65 Global Reset to I/O Register Latch
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.
— 13.7 — 16.4 ns
15
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