ISPGDX160V-3Q208I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
ISPGDX160V-3Q208I Datasheet PDF : 36 Pages
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Specifications ispGDX160V
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST1 #
COND.
DESCRIPTION
tpd
tsel
S fmax (Tog.)
fmax (Ext.)
tsu1
E tsu2
tsu3
IC tsu4
D tsuce1
tsuce2
V tsuce3
E th1
th2
E U th3
th4
D thce1
IN thce2
thce3
T tgco1
T tgco2
tco1
C N tco2
ten
E tdis
O ttoeen
L ttoedis
E C twh
twl
S IS trst
trw
tsl
D tsk
A 1 Data Prop. Delay from Any I/O pin to Any I/O pin (4:1 MUX)
A 2 Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)
– 3 Clock Frequency, Max. Toggle
–
4
Clock Frequency with External Feedback (
1
tsu3+tgco1
)
– 5 Input Latch or Register Setup Time Before Yx
– 6 Input Latch or Register Setup Time Before I/O Clock
– 7 Output Latch or Register Setup Time Before Yx
– 8 Output Latch or Register Setup Time Before I/O Clock
– 9 Global Clock Enable Setup Time Before Yx
– 10 Global Clock Enable Setup Time Before I/O Clock
– 11 I/O Clock Enable Setup Time Before Yx
– 12 Input Latch or Register Hold Time (Yx)
– 13 Input Latch or Register Hold Time (I/O Clock)
– 14 Output Latch or Register Hold Time (Yx)
– 15 Output Latch or Register Hold Time (I/O Clock)
– 16 Global Clock Enable Hold Time (Yx)
– 17 Global Clock Enable Hold Time (I/O Clock)
– 18 I/O Clock Enable Hold Time (Yx)
A 19 Output Latch or Register Clock (from Yx) to Output Delay
A 20 Input Latch or Register Clock (from Yx) to Output Delay
A 21 Output Latch or Register Clock (from I/O pin) to Output Delay
A 22 Input Latch or Register Clock (from I/O pin) to Output Delay
B 23 Input to Output Enable
C 24 Input to Output Disable
B 25 Test OE Output Enable
C 26 Test OE Output Disable
– 27 Clock Pulse Duration, High
– 28 Clock Pulse Duration, Low
– 29 Register Reset Delay from RESET Low
– 30 Reset Pulse Width
D 31 Output Delay Adder for Output Timings Using Slow Slew Rate
A 32 Output Skew (tgco1 Across Chip)
-5
-7
UNITS
MIN. MAX. MIN. MAX.
– 5.0 – 7.0 ns
– 6.5 – 9.0 ns
143 – 100 – MHz
110 – 80.0 – MHz
4.0 – 5.5 – ns
3.0 – 4.5 – ns
4.0 – 5.5 – ns
3.0 – 4.5 – ns
2.5 – 3.5 – ns
1.5 – 2.5 – ns
4.5 – 6.5 – ns
0.0 – 0.0 – ns
1.5 – 2.5 – ns
0.0 – 0.0 – ns
1.5 – 2.5 – ns
0.0 – 0.0 – ns
1.5 – 2.5 – ns
0.0 – 0.0 – ns
– 5.0 – 7.0 ns
– 8.5 – 11.0 ns
– 6.0 – 9.0 ns
– 9.5 – 13.0 ns
– 6.0 – 8.5 ns
– 6.0 – 8.5 ns
– 9.0 – 12.0 ns
– 9.0 – 12.0 ns
3.5 – 5.0 – ns
3.5 – 5.0 – ns
– 14.0 – 18.0 ns
10.0 – 14.0 – ns
– 8.0 – 12.0 ns
– 0.5 – 0.5 ns
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
18
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