STA323WQS13TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STA323WQS13TR

2.1-channel high-efficiency digital audio system with QSound QHD®

STMicroelectronics 

I2C bus specification

6

I2C bus specification

STA323WQS

The STA323WQS supports the I2C fast mode (400 kbit/s) protocol. This protocol defines

any device that sends data on to the bus as a transmitter and any device that reads the data

as a receiver. The device that controls the data transfer is known as the master and the

other as the slave. The master always starts the transfer and provides the serial clock for

synchronization. The STA323WQS is always a slave device in all of its communications.

6.1

Communication protocol

Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition

while the clock is high is used to identify a START or STOP condition.

Start condition

START is identified by a high to low transition of the data bus SDA signal while the clock

signal SCL is stable in the high state. A START condition must precede any command for

data transfer.

Stop condition

STOP is identified by a low to high transition of the data bus SDA signal while the clock

signal SCL is stable in the high state. A STOP condition terminates communication between

STA323WQS and the bus master.

Data input

During the data input the STA323WQS samples the SDA signal on the rising edge of clock

SCL. For correct device operation the SDA signal must be stable during the rising edge of

the clock and the data can change only when the SCL line is low.

6.2

Device addressing

To start communication between the master and the STA323WQS, the master must initiate

with a START condition. Following this, the master sends 8 bits (MSB first) on the SDA line

corresponding to the device select address and read or write mode.

The 7 MSBs are the device address identifiers, corresponding to the I2C bus definition. In

the STA323WQS the I2C interface uses a device address of decimal 34 (binary 00100010).

The 8th bit (LSB) identifies read or write operation, RW. This bit is set to 1 in read mode and

0 for write mode. After a START condition the STA323WQS identifies the device address on

the bus. If a match is found, it acknowledges the identification on the SDA bus during the 9th

bit time. The byte following the device identification byte is the internal space address.

34/78

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