STA323WQS13TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA323WQS13TR Datasheet PDF : 78 Pages
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Register descriptions
STA323WQS
Table 13. Register summary (continued)
Address Name
D7
D6
D5
D4
D3
D2
D1
0x20
A2cf1 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17
0x21
A2cf2 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9
0x22
0x23
A2cf3
B0cf1
C4B7
C5B23
C4B6
C5B22
C4B5
C5B21
C4B4
C5B20
C4B3
C5B19
C4B2
C5B18
C4B1
C5B17
0x24
B0cf2 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9
0x25
B0cf3
C5B7
C5B6
C5B5
C5B4
C5B3
C5B2
C5B1
0x26
Cfud
WA
0x27
0x28
MPCC1 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9
MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1
0x29
RES
RES
RES
RES
RES
RES
RES
RES
0x2A
RES
RES
RES
RES
RES
RES
RES
RES
0x2B
FDRC1 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9
0x2C
0x2D
FDRC2
Status
FDRC7
PLLUL
FDRC6
FDRC5
FDRC4
FDRC3
FDRC2
FDRC1
FAULT
D0
C4B16
C4B8
C4B0
C5B16
C5B8
C5B0
W1
MPCC8
MPCC0
RES
RES
FDRC8
FDRC0
TWARN
7.1
7.1.1
Configuration register A (address 0x00)
D7
D6
D5
D4
FDRB
TWAB
TWRB
IR1
0
1
1
0
D3
D2
D1
D0
IR0
MCS2
MCS1
MCS0
0
0
1
1
Master clock select
Table 14. Master clock select
Bit R/W RST Name
Description
0 RW 1
1 RW 1
2 RW 0
MCS0
MCS1
MCS2
Master clock select: selects the ratio between the input
I2S sample frequency and the input clock.
The STA323WQS supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and
96 kHz. Therefore the internal clock is:
" 32.768 MHz for 32 kHz
" 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
" 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
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