STA323WQS13TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA323WQS13TR Datasheet PDF : 78 Pages
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STA323WQS
6.3
Write operation
Figure 46. I2C write procedure
I2C bus specification
BYTE
WRITE
START
MULTIBYTE
WRITE
START
DEV-ADDR
DEV-ADDR
ACK
RW
ACK
RW
SUB-ADDR
ACK
SUB-ADDR
ACK
DATA IN
DATA IN
ACK
STOP
ACK
DATA IN
ACK
STOP
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA323WQS acknowledges this and then the master writes the internal address
byte.
After receiving the internal byte address the STA323WQS again responds with an
acknowledgement.
Byte write
In the byte write mode the master sends one data byte. This is acknowledged by the
STA323WQS. The master then terminates the transfer by generating a STOP condition.
Multi-byte write
The multi-byte write modes can start from any internal address. Sequential data bytes are
written to sequential addresses within the STA323WQS.
The master generates a STOP condition to terminate the transfer.
6.4
Read operation
Figure 47. I2C read procedure
CURRENT
ADDRESS
READ
START
RANDOM
ADDRESS
READ
START
SEQUENTIAL
CURRENT
READ
START
SEQUENTIAL
RANDOM
READ
START
ACK
DEV-ADDR
DEV-ADDR
RW
ACK
DEV-ADDR
RW
RW= ACK
HIGH
DEV-ADDR
ACK
RW
DATA
SUB-ADDR
DATA
NO ACK
STOP
ACK
DEV-ADDR
START
ACK
DATA
ACK
RW
ACK
SUB-ADDR
ACK
START
DEV-ADDR
ACK
RW
DATA
DATA
DATA
NO ACK
STOP
NO ACK
ACK
STOP
DATA
ACK
DATA
NO ACK
STOP
Current address byte read
Following the START condition the master sends a device select code with the RW bit set
to 1. The STA323WQS acknowledges this and then responds by sending one byte of data.
The master then terminates the transfer by generating a STOP condition.
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