ST92F250CV2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F250CV2

8/16-bit single voltage Flash MCU family with RAM, E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD

STMicroelectronics 

Single voltage Flash and E3™ (emulated EEPROM)

1: Select protection

Bit 0 = FBUSY: Flash Busy (Read Only).

This bit is automatically set during Page Program, Byte Program, Sector Erase or Set

Protection operations when the first address to be modified is latched in Flash memory, or

during Chip Erase operation when bit FWMS is set. When this bit is set every read access to

the Flash memory will output invalid data (FFh equivalent to a NOP instruction), while every

write access to the Flash memory will be ignored. At the end of the write operations or

during a Sector Erase Suspend this bit is automatically reset and the memory returns to

read mode. After an Erase Resume this bit is automatically set again. The FBUSY bit

remains high for a maximum of 10μs after Power-Up and when exiting Power-Down mode,

meaning that the Flash memory is not yet ready to be accessed.

0: Flash not busy

1: Flash busy

E3 TM CONTROL REGISTER (ECR)

Address: 224001h /221001h- Read/Write

Reset value: 000x x000 (xxh)

7

6

5

4

EWMS

EPAGE

ECHIP

3

2

1

0

WFIS

FEIEN

EBUSY

The E3 TM Control Register is used to enable all the operations for the E3 TM memory.

The ECR also contains two bits (WFIS and FEIEN) that are related to both Flash and E3 TM

memories.

Bit 7 = EWMS: E3 TM Write Mode Start.

This bit must be set to start every write/erase operation in the E3 TM memory. At the end of the

write/erase operation this bit is automatically reset. Resetting by software this bit does not

stop the current write operation.

0: No effect

1: Start E3 TM write

Bit 6 = EPAGE: E3 TM page update.

This bit must be set to select the Page Update operation in E3 TM memory. The Page Update

operation allows to write a new content: both “0”s in place of “1”s and “1”s in place of “0”s.

From 1 to 16 bytes can be entered (in any order, no need for an ordered address sequence)

before starting the execution by setting bit EWMS. All the addresses must belong to the

same page (only the 4 LSBs of address can change). Data to be programmed and

addresses in which to program must be provided (through an LD instruction, for example).

Data contained in page addresses that are not entered are left unchanged. This bit is

automatically reset at the end of the Page Update operation.

0: Deselect page update

1: Select page update

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Doc ID 8848 Rev 7

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