ST92F250CV2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F250CV2

8/16-bit single voltage Flash MCU family with RAM, E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD

STMicroelectronics 

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2Single voltage Flash and E3™ (emulated

Bit 5 = ECHIP: E3 TM chip erase.

This bit must be set to select the Chip Erase operation in the E3 TM memory. The Chip Erase

operation allows to erase all the E3 TM locations to FFh. The execution starts by setting bit

EWMS. This bit is automatically reset at the end of the Chip Erase operation.

0: Deselect chip erase

1: Select chip erase

Note:

Bit 4:3 = Reserved.

Bit 2 = WFIS: Wait For Interrupt Status.

If this bit is reset, the WFI instruction puts the Flash macrocell in Stand-by mode (immediate

read possible, but higher consumption: 100 μA); if it is set, the WFI instruction puts the Flash

macrocell in Power-Down mode (recovery time of 10μs needed before reading, but lower

consumption: 10μA). The Stand-by mode or the Power-Down mode will be entered only at

the end of any current Flash or E3 TM write operation.

In the same way following an HALT or a STOP instruction, the Memory enters Power-Down

mode only after the completion of any current write operation.

0: Flash in Stand-by mode on WFI

1: Flash in Power-Down mode on WFI

HALT or STOP mode can be exited without problems, but the user should take care when

exiting WFI Power Down mode. If WFIS is set, the user code must reset the XT_DIV16 bit in

the R242 register (page 55) before executing the WFI instruction. When exiting WFI mode,

this gives the Flash enough time to wake up before the interrupt vector fetch.

Bit 1 = FEIEN: Flash & E3 TM Interrupt enable.

This bit selects the source of interrupt channel

INTx between the external interrupt pin and the Flash/E3 TM End of Write interrupt. Refer to

the Interrupt chapter for the channel number.

0: External interrupt enabled

1: Flash & E3 TM Interrupt enabled

Bit 0 = EBUSY: E3 TM Busy (Read Only).

This bit is automatically set during a Page Update operation when the first address to be

modified is latched in the E3 TM memory, or during Chip Erase operation when bit EWMS is

set. At the end of the write operation or during a Sector Erase Suspend this bit is

automatically reset and the memory returns to read mode. When this bit is set every read

access to the E3 TM memory will output invalid data (FFh equivalent to a NOP instruction),

while every write access to the E3 TM memory will be ignored. At the end of the write operation

this bit is automatically reset and the memory returns to read mode. Bit EBUSY remains

high for a maximum of 10ms after Power-Up and when exiting Power-Down mode, meaning

that the E3 TM memory is not yet ready to be accessed.

0: E3 TM not busy

1: E3 TM busy

Doc ID 8848 Rev 7

83/523

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