Single voltage Flash and E3™ (emulated EEPROM)
7.3.2
Status registers
Two Status Registers (FESR[1:0] are available to check the status of the current write
operation in Flash and E3 TM memories.
During a Flash or an E3 TM write operation any attempt to read the memory under modification
will output invalid data (FFh equivalent to a NOP instruction). This means that the Flash
memory is not fetchable when a write operation is active: the write operation commands
must be given from another memory (E3 TM, internal RAM, or external memory).
FLASH & E3 TM STATUS REGISTER 0 (FESR0)
Address: 224002h /221002h -Read/Write
Reset value: 0000 0000 (00h)
7
6
5
4
3
FEERR FESS6 FESS5 FESS4 FESS3
2
FESS2
1
FESS1
0
FESS0
Bit 7 = FEERR: Flash or E3 TM write ERRor (Read/Write).
This bit is set by hardware when an error occurs during a Flash or an E3 TM write operation. It
must be cleared by software.
0: Write OK
1: Flash or E3 TM write error
Bit 6:0 = FESS[6:0]. Flash and E3 TM Sectors Status Bits (Read Only).
These bits are set by hardware and give the status of the 7 Flash and E3 TM sectors.
● FESS6 = TestFlash and OTP
● FESS5:4 = E3 TM sectors
For 128K and 64K Flash devices:
● FESS3:0 = Flash sectors (F3:0)
For the ST92F250 (256K):
● FESS3 gives the status of F5, F4 and F3 sectors: the status of all these three sectors
are ORed on this bit
● FESS2:0 = Flash sectors (F2:0)
The meaning of the FESSx bit for sector x is given in Table 12.
Table 12. Sector status bits
FEERR
FBUSY
EBUSY
FSUSP
FESSx=1 meaning
1
-
-
Write Error in Sector x
0
1
-
Write operation on-going in sector x
0
0
1
Sector Erase Suspended in sector x
0
0
0
Don’t care
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Doc ID 8848 Rev 7