FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.1.2.5

3.1.2.6

3.1.2.7

Transmitter Output Voltage

The drivers are terminated in a 25 ? load, obtained by two 50 ? in

parallel. The single-ended voltage swing, VSW, is determined

multiplying the driver current, IDR, by this impedance.

Driver Termination Voltage

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VTCM = VIT - VSW

The

and

Output

VSW:

High

and

Output

Low

voltages

are

also

determined

by

VTT

VOH = VIT - 0.5*VSW

VOL = VIT - 0.5*VSW

There is a limit placed on VSW by

various settings of VTT are given

itnhTeaVbTleT

setting.

2. VSW

The limits

should be

oconnVtrSoWllefodr

by setting the High Drive and Low Drive bits of the SERDES_CNTL_2

register and the DTX bits of the SERDES_CNTL_1 register.

Table 2.

VTT and Max Allowable VSW

VTT (V)

1.0

1.2

1.5

1.8

Max VSW (AC, mV)

250

350

500

750

Receiver Clock and Data Recovery

Clock and Data recovery (CDR) at the receiver of the FM2112 is

dependent on two factors. One is the ppm difference in the clock

frequencies between the transmitting device and the FM2112's

receiver. The other is the bit transition density in the data stream.

The lock time of the CDR circuit is dependent on the ppm difference in

clock frequencies and the transition density. Given a 1 in 10 transition

density (XAUI signals meet this criterion), the CDR lock times are given

in Table 3 for several ppm differences.

Table 3.

CDR Lock Times

Clock PPM Difference

0

CDR Lock Time (Bit Periods)

640

22

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