FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

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Description

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FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.1.6.3

• If the pause feature is off, whether the switch should discard or trap MAC control

frames to the CPU

• Number of 512 bit times specified in the Tx Pause message

• Time between Pause messages sent by the Tx to the upstream link partner, when

the port is “paused” by the congestion management watermarks.

• The port MAC address which is the source address in a Pause message.

The policy for when a port is paused is described in 3.3.

Proprietary Header Support

{Described in registers Table 72 and Table 155}

This is not an IEEE compliant feature, but is generally considered useful

for interconnecting XAUI-based ASICs which are not fully IEEE

compliant.

The feature is illustrated in Figure 7. It has two components. There is a

header offset, which allows the MAC to skip up to 255 bytes (in 4-word

increments) before interpreting the next 16 bytes as the actual

switching header. Secondly, there is a 128 bit mask that covers any

aspect of the header that the switch should ignore (it sets the masked

bits to zero internally). Finally, any standard Ethernet feature that is

undesired must be turned off.

This enables:

• Pre-pended header information (which the switch can ignore)

• Switching and link aggregation hashing from any field in the header

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