FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

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FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.1.6

However, this capability has not been defined, and is beyond the scope

of the feature in this generation of the Intel®Ethernet Switch Family

architecture.)

Priority Pacing

10G improves latency over 1G because it takes 1/10 the time to

transmit a frame. So even if a server doesn't need 10G, it may be

desirable to have a 10G connection for low latency. Pacing is used to

control the bandwidth to a level that the server can consume. There is

a catch though: if a high priority frame follows a low priority frame,

then it experiences a delay equal to the length of the low priority frame

plus the IFG stretch. In the case of sustained low priority bandwidth,

the high priority frame will always find itself behind a low priority

frame, and will always get stuck behind the IFGS, which could

completely nullify the latency advantage of going to the 10G link.

To mitigate this adverse effect, the link can be configured to run ahead

of the pacing rate by a finite amount. This is unavoidable during the

transmission of a packet, which must proceed at 10 Gbps. A packet

should not be dropped by the downstream link partner provided that

over the time interval T, BW ≤ PR*T+C, where C is a constant that

represents a reserved amount of space in the downstream link

partner's frame buffer. As a latency optimization, priority is taken into

account in determining when to repay the accumulated IFGS.

Counter Implementation

The IFGS is implemented with a counter, which operates with the

following rules:

• Every time a frame is transmitted the length of the frame is added to the counter.

• Over time-interval T, 10 Gbps * PR*T is subtracted from the counter.

• The value of T is 1024 bytes. This will cause a jitter of +/- 800ns. The maximum

pacing rate is 1/256th of the line rate. The precision is 0.4% of a 10 Gbps link.

• The counter may not go below zero. The counter may go as high as the max WM +

Max frame size.

There are watermarks per priority. On transmission of a new frame, the

counter is checked against the watermark for that frame's IEEE 802.1p

priority. If the counter is below the watermark, the frame is

transmitted, if the counter is above the watermark, the frame is not

transmitted. After the counter is decremented, the watermark is

checked again. This check is independent of the minimum inter-frame

gap check that all packets must meet.

MAC

{Described in registers Table 155 and Table 156}

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