FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.1.4

3.1.4.1

Each SerDes lane has one (BIST) transmitter and one BIST checker.

The supported BIST modes are:

• 0 - Disable

• 1 - PRBS (x9+x5+x1), repeat every 511 cycles

• 2 - High frequency test data = 1010101010

• 3 - Test data = K28.5 (IDLE)

• 4 - Low frequency test data = 0001111100

• 5 - PRBS (x10+x3+x1), repeat every 1023 cycles

• 6 - PRBS (x9+x4+x1), repeat every 511 cycles

• 7 - PRBS (x7+x1), repeat every 127 cycles

The BIST transmitters on all 4 lanes are automatically enabled when

the BIST mode is set to a value different than 0. The BIST checkers are

activated by writing a 0 into SERDES_TEST_MODE[BS]. The values in

BIST_ERR_CNT count the number of errors received per lane.

The BIST checker will work properly only if symbols are aligned prior to

start the checker. The symbol alignment is done by the PCS framer

using the comma character as a reference which is the only character

to use a series of five 1s or 0s in the normal flow of data. However, as

the BIST transmitter may generate this test pattern, it is important to

follow the following procedure:

• Obtain symbol lock prior to enabling BIST transmitter (bits 3-0 of

SERDES_STATUS)

• Disable PCS framer (bit 6 of SERDES_TEST_MODE)

• Set BIST mode (which automatically enabled the transmitter as well)

• Enable BIST checker (bit 5 of SERDES_TEST_MODE)

• Verify BIST_ERR_CNT to detect any error

PCS

{Registers described in Table 145 through Table 151.}

The PCS is fully compliant to the following specifications:

• IEEE 802.3ae Clause 48 (10GBase-X) specification for XAUI mode

• IEEE 802.3-2002 Clause 36 (1000Base-X) specification for SGMII mode

PCS - Frame Format

The frame format in 10G mode is show in the next table. The value of

Dp (Data preamble) is 55h (symbol D21.2), the value of Ds (Data start)

is D5h (symbol D21.6). The PCS layer always expect a strict 8-symbol

preamble (includes 1x|S|, 6x|Dp| and 1x|Ds|).

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