FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.3.1.1

3.3.2

Note:

Figure 10. Priority Mapping

Priority Regeneration

The FM2112 supports priority regeneration where the ingress priorities

map to different egress priorities. Up to 8 priorities can be remapped

without having any effect on the other PWD or egress scheduling

priorities. To remap a priority, the Ingress VLAN priority is mapped to a

switch priority 8-15 and that priority is configured with the desired

egress priority. The mapping to PWD and egress scheduling must still

be configured as they were in switch priorities 0-7.

Shared Memory Queues

{Described in registers Table 101 through Table 107, Table 110 and

Table 111}

Weights assigned to queues in Strict Priority mode have no relevance.

The FM2112's shared memory architecture allows the construction of

queues of variable sizes. A memory segment in the Intel®Ethernet

Switch Family has an “association” with multiple queue resources. This

association is used to track queue status on which PWD and Pause are

based.

There are three types of status or “segment association” reported by

the switch element. They are RX port, TX port, and shared pool.

• A segment maintains its RX and global association from when the memory is

initially allocated to when it is freed after transmission.

• The TX port association is established once the forwarding information for that

frame is determined, and it is freed after transmission. In multicast, it is freed after

transmission to the last port.

45

Share Link: