FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

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Description

Manufacturer

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.3.3.2

GHD (Global High Discard). PWD is applied to GHD. GHD should be greater than

GLD.

• The Global Privilege watermark is exceeded: g > GPD (Global Privilege Discard)

—>100% packet drop. This is set to the highest watermark. In this case, g is taken

as the total memory used. Not just the memory in the shared pool.

PWD Calculation

The algorithm for PWD is

• Compute the occupancy level at which 100% drop begins for the priority in

question

— The priority is the internal switch priority as determined by RX_PRI_MAP

— The queue occupancy is the actual occupancy in KB of the shared memory and

excludes the private per-port queue.

— In the Intel®Ethernet Switch Family there is only one PWD calculation per

packet, even though there are multiple watermark checks.

The equations describing the drop characteristics are:

Equation 1

3.3.4

Where:

• WM - Watermark: either GLD or GHD watermarks (See Table 104)

• x - status value for the queue

• s - PWD slope configuration - 4 bit quantity (see Table 97 and Table 98).

Pause Flow Control

The FM2112 is fully compliant with IEEE 802.3x, and IEEE 802.3-2002

clause 31 and Annex 31a and Annex 31b.

The Intel®Ethernet Switch Family will signal pause-on for two reasons.

Either a single port has exceeded its max allotment of the shared

memory, or the global memory is too full and the port has exceeded its

private memory allotment. This is defined with the following equations:

48

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