FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

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FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

Equation 2

The global watermark default (see Note: Weights assigned to queues in

Strict Priority mode have no relevance,Table 110) is 0x144,

corresponding to 324 kB, or about 13.8 kB per port. Private watermark

default (see Table 102) is 16.4 kB per port. The condition for signaling

pause-on where a port exceeds its private watermark while the global

watermark is also exceeded is:

1024kB (total memory) - [13kB (global WM) x 24 ports] - [16kB

(default RxPvi) x 24]

which leaves 300 kB unused in the switch, or about 12.5kB/port. For

lossless flow control, 2 packets of 2kB each must be stored, leaving

over 8kB per port of “wire delay” or “bytes in flight” that can be stored.

Where the following are defined as:

• pausei - The pause state of the ith port.

• rxi - Number of active 1024 byte segments associated with the Rx of port i.

• RxsPih - Rx shared pause-on watermark for the ith port.

• RxsPil - Rx shared pause-off watermark for the ith port.

• GPh - Global Pause-on watermark.

• GPl - Global Pause-off watermark.

• RxPvi - Rx private watermark for the ith port.

The rate of signaling pause messages is independent of the status

crossing the pause on/off watermarks, and separately configured.

The Intel®Ethernet Switch Family supports the following Pause

features:

• Pause on/off based on Equation 2.

• Configurable Pause timer

• Configurable Pause watermarks, including configurable hysteresis between on and

off.

• Asymmetric Pause

— Rx may respond to Pause while TX never transmits pause messages.

— Rx may be configured to ignore Pause while TX produces pause messages.

— Both Rx and Tx may be configured to ignore pause and not transmit pause

— Both Rx and Tx may be configured to respect pause and transmit pause as

specified in IEEE 802.3x

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