FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.3.5.1

3.4

Credit Adding

• In strict priority there is no need to ever add credits

• In WRR credits are added depending on the service algorithm

— PO - The ESPQ gains its weight of credits once there are no credits left for all

eligible ESPQs

— PRR - All ESPQs are reset to their weight once there are no more credits in any

ESPQ

Weights, Queues and Configuration

• There are 4 ESPQs per port

• Each ESPQ has a 8 bit weight, giving a range of 1-255. The value 0 is illegal.

• The default is strict priority

• Each ESPQ has a configuration between strict and WRR

• For all the WRR ports, the global service algorithm is configurable between PO and

PRR.

Jitter Buffers

{Described in register Table 114}

The FM2112 has jitter buffers on either side of the switch element

datapath (SED) to prevent RX overflow and TX underflow.

Size and Configuration

• RX jitter buffer

— 256 bytes

— No configuration

• TX jitter buffer

— 256 bytes

— Cut-through Watermark configurable from 8 to 256 bytes in word increments

— Store-n-Forward Watermark configurable from 8 to 256 bytes in word

increments

• Latency

— The RX jitter buffer adds 50 ns latency (one 64-byte subsegment) to packet

transmission regardless of size.

— The TX jitter buffer adds no more latency than its size / data-rate as configured

by the watermarks.

— However, the last 64 byte segment of a packet is scheduled irrespective of the

occupancy assuming the occupancy is greater than 8 bytes. A 64 byte frame is

therefore transmitted without an occupancy-watermark check.

Statistics

{Described in registers Table 117 through Table 129}

51

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