FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

• SWITCH MGMT (Slave)

• PORT MGMT (Slave)

Figure 12 shows the management infrastructure.

Figure 12. Intel®Ethernet Switch Family Management Infrastructure

A master component is a component capable of issuing commands

(read or write) on the management bus, a slave component is a

component capable to receive such commands and execute but is not

capable to generate one.

The components are defined here and detailed in the next sections:

CPU Interface:

The interface used by a local CPU to manage the device.

JTAG:

The interface used to access the boundary scan chain or the

internal scan chains (diagnostic or RAM repair).

JTAG2MGMT:

A bridge from JTAG to the internal bus. The bridge allows an

external device connected to the JTAG interface to access the

internal management bus and thus any slave device on that bus.

MGMT2JTAG:

A bridge from the internal bus to JTAG. The bridge allows a bus

master (CPU Interface, BOOT FSM, or EEPROM) to access

internal scan chains.

LCI:

Logical CPU Interface. The port used to send or receive packets

from the switch.

SPI:

Serial Port Interface. An interface to an external serial EEPROM.

53

Share Link: