FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

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FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

Packet reception with an external DMA controller is shown in Figure 15.

The RXREQ signal replicates the RXRDY bit of the LCI_STATUS register

and is asserted whenever the Intel®Ethernet Switch Family has a data

word available to the CPU. The DMA controller can read data words

from packet as long as the signal is asserted. The RXEOT signal is

automatically asserted when the last word of a packet is being read

(this last word contains the packet length, the source port and the CRC

status). The EOT signal allows a DMA controller that has buffer chaining

capability to automatically close the current buffer and move to the

next one for the next packet without CPU intervention.

The Intel®Ethernet Switch Family has the option to pad the frames to

either a 32 bit boundary or a 64-bit boundary. The last 32 bits always

contains the status work.

3.5.1.3

Figure 15. Frame Reception

Implementation notes: It is important that RXREQ is de-asserted at the

beginning of the read cycle when there are no more frames in the

queue as shown in the figure. This will give enough heads up to the

DMA to not start another transfer immediately. The recommend

behavior is to de-assert RXREQ only at the end of the frame and at the

same time as EOT is asserted and data is driven.

Little and Big Endian Support

The endianness only affects the position of the bytes within one word.

In a big endian processor, the successive bytes of a packet must be

stored starting by placing the first byte in the most significant byte

location of the memory and moving right. In a little endian processor,

the successive bytes of a packet must be store starting by placing the

first byte in the least significant byte location and moving left. In the

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