FBFM2112F897CSLJLS View Datasheet(PDF) - Intel
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FBFM2112F897CSLJLS Datasheet PDF : 169 Pages
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Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet
3.5.1.2
• Write the destination mask into the LCI_TX_FIFO register as described in Table 11.
• Write frame payload words into the LCI_TX_FIFO register. The last word shall be
padded by the host if the frame length is not a multiple of 4 bytes.
Packet reception
• Check that the receiver has data by polling the RXRDY bit of the LCI_STATUS
register
— The CPU can enable an interrupt to wait for data.
• Read LCI_RXFIFO.
— There are three ways to indicate packet completion.
—The CPU can enable an interrupt to inform it that a packet has finished being
sent to it.
—Read the EOT bit in the LCI_STATUS register every time that LCI_RXFIFO is
read. The EOT bit indicates end of transmission.
—Observe the EOT pin on the CPU interface.
—The second to the last word is the end of the packet data, and it is padded to
32 bits.
—The last word does not contain any packet data. It is an in-band status word.
Its definition is contained in the table RX_FRAME_STATUS.
Packet Transmission and Reception with a DMA Controller
Packet transmission with an external DMA controller is shown in
Figure 14. The external TXRDY_N signal replicates the TXRDY bit of the
LCI_STATUS register and is asserted whenever the Intel®Ethernet
Switch Family can accept a packet word from the CPU. The DMA
controller may transfer data words as long as this signal is asserted.
Figure 14. Frame Transmission
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