FBFM2112F897CSLJLS View Datasheet(PDF) - Intel
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FBFM2112F897CSLJLS Datasheet PDF : 169 Pages
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Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet
3.5.1.4
In-band Control Word Definitions
LCI_RX_FRAME_STATUS is appended to the end of a data transmission.
Thus the amount of memory taken up in the receive buffer in the host
CPU is the packet length + 4 bytes. LCI_TX_DMASK and LCI_TX_LEN
are control words inserted in-band on data transmission. Note that
even if the CPU forwarding mode is “forward normally” The control
word LCI_TX_DMASK is still assumed to be the second word. In this
case it is just ignored.
Table 8.
LCI_RX_EXTRA_INFO
Name
SrcPort
VLAN Action
Bit
23:18
17:16
Description
Indicates on which port the switch received
this frame.
Indicates how the VLAN ID shall be
interpreted.
Type
Default
0: Do nothing, the VLAN ID indicated in this
register is the same as the VLAN ID in the
frame.
1: The VLAN ID indicated in this register is
the new VLAN association for this frame and
the VLAN tag present in this frame shall be
removed.
2: The VLAN ID indicated in this register is
the new VLAN association for this frame and
shall be added to this frame.
Priority
VLAN ID
RSVD
3: The VLAN ID indicates in this register is
the new VLAN association for this frame and
shall replace the one present in the frame.
15:12
Indicates the internal switch priority
associated with this frame.
11:0 Indicates the VLAN association for this frame. RO
0
31:24 Reserved. Set to 0.
RV
0
Table 9.
LCI_RX_FRAME_STATUS
Name
Padding
Underflow
Tail Error
Bad CRC
RSVD
Bit
5:3
2
1
0
30:6
Description
Type
The number of bytes in the last word that are RO
not valid
There was an underflow during this frame on RO
the TX side.
The error bit in the fabric was set for this
RO
frame.
Packet had a bad CRC
RO
Reserved. Set to 0.
RV
Default
0
0
0
0
0
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