FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.5

The FM2112 keeps packet statistics compliant with IETF RFC 2819, and

additional statistics for proprietary features. The general principle is

“any time a switch takes action on a frame, count the action.

Statistics are divided into groups. Only one counter within a group is

exercised on any given frame. See section 5.7 for a complete list of the

counters. The groups are:

• RMON RX frames by type

• RMON RX frames by size

• RMON RX octets

• RMON RX frame by priority

• RMON RX octets by priority

• RX forwarding action

• RMON TX frames by type

• RMON TX frames by size

• RMON TX octets

• Switch frame drops by Congestion Management

• Switch frame forwarded by VLAN

• Switch bytes forwarded by VLAN

• Switch Triggers

All counters in the Intel®Ethernet Switch Family are 64 bits. There is no

event rate requirement for reading the statistics for even the byte

counters on the order of the lifetime of the chip. The counters are read

32 bits at a time. Bandwidth over the CPU interface may be saved by

reading only the lower 32 bits of the counters.

There are other counters in the chip for debug purposes in both the EPL

and the MAC table status. See their respective sections for a

description of their debug counters.

Counters may be reset to 0 by executing a write access into the

counter. The 64-bit counters are reset to 0 regardless of which 32-bit

word (high or low) is written and the value written is a don't care.

Management

The chip management block includes the following components:

• BOOT FSM (Master/Slave)

• LCI (Slave)

• SPI (Master)

• CPU Interface (Master)

• JTAG (Master)

• LED (Master)

• JTAG2MGMT (Master)

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