Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet
3.5.1.1
Figure 13. Example of Intel®Ethernet Switch Family with a PCI DMA Controller
Packet Transmission and Reception without a DMA Controller
In absence of DMA controller, the data transfer protocol is the
following:
Packet transmission
• Check that the transmitter is ready by reading the TXRDY bit of the LCI_STATUS
register. If not ready, either poll this bit until the transmitter is ready or enable an
interrupt to wait for this status.
• Write the packet length word into the LCI_TX_FIFO register as described in
Table 76.
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