PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
REGISTER 23-14: C1RXFn: CAN ACCEPTANCE FILTER ‘n’ REGISTER (‘n’ = 0 THROUGH 15)
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
23:16
15:8
7:0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID<2:0>
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID<10:3>
U-0
R/W-0
—
EXID
R/W-x
R/W-x
EID<15:8>
R/W-x
R/W-x
EID<7:0>
R/W-x
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID<17:16>
R/W-x
R/W-x
R/W-x
R/W-x
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-21
bit 20
bit 19
bit 18
bit 17-0
SID<10:0>: Standard Identifier bits
1 = Message address bit SIDx must be ‘1’ to match filter
0 = Message address bit SIDx must be ‘0’ to match filter
Unimplemented: Read as ‘0’
EXID: Extended Identifier Enable bits
1 = Match only messages with extended identifier addresses
0 = Match only messages with standard identifier addresses
Unimplemented: Read as ‘0’
EID<17:0>: Extended Identifier bits
1 = Message address bit EIDx must be ‘1’ to match filter
0 = Message address bit EIDx must be ‘0’ to match filter
Note: This register can only be modified when the filter is disabled (FLTENn = 0).
DS60001290E-page 264
2014-2017 Microchip Technology Inc.