PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 23-16: C1FIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (‘n’ = 0 THROUGH 15)

Bit

Range

31:24

23:16

15:8

7:0

Bit

31/23/15/7

U-0

—

U-0

—

U-0

—

R/W-0

TXEN

Bit

30/22/14/6

U-0

—

U-0

—

S/HC-0

FRESET

R-0

TXABAT(2)

Bit

29/21/13/5

U-0

—

U-0

—

S/HC-0

UINC

R-0

TXLARB(3)

Bit

28/20/12/4

U-0

—

R/W-0

R/W-0

DONLY(1)

R-0

TXERR(3)

Bit

Bit

Bit

Bit

27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0

U-0

U-0

U-0

U-0

—

—

—

—

R/W-0

R/W-0

R/W-0

FSIZE<4:0>(1)

R/W-0

U-0

U-0

U-0

U-0

—

—

—

—

R/W-0

TXREQ

R/W-0

RTREN

R/W-0

R/W-0

TXPR<1:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-21 Unimplemented: Read as ‘0’

bit 20-16 FSIZE<4:0>: FIFO Size bits(1)

11111 = Reserved

•

•

•

10000 = Reserved

01111 = FIFO is 16 messages deep

•

•

•

00000 = FIFO is 1 message deep

bit 15 Unimplemented: Read as ‘0’

bit 14 FRESET: FIFO Reset bits

1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user should

poll whether this bit is clear before taking any action.

0 = No effect

bit 13 UINC: Increment Head/Tail bit

TXEN = 1: (FIFO configured as a Transmit FIFO)

When this bit is set the FIFO head will increment by a single message

TXEN = 0: (FIFO configured as a Receive FIFO)

When this bit is set the FIFO tail will increment by a single message

bit 12 DONLY: Store Message Data Only bit(1)

TXEN = 1: (FIFO configured as a Transmit FIFO)

This bit is not used and has no effect.

TXEN = 0: (FIFO configured as a Receive FIFO)

1 = Only data bytes will be stored in the FIFO

0 = Full message is stored, including identifier

bit 11-8 Unimplemented: Read as ‘0’

Note 1:

2:

3:

These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits

(C1CON<23:21>) = 100).

This bit is updated when a message completes (or aborts) or when the FIFO is reset.

This bit is reset on any read of this register or when the FIFO is reset.

DS60001290E-page 266

 2014-2017 Microchip Technology Inc.

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