PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 23-16: C1FIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (‘n’ = 0 THROUGH 15)

bit 7

TXEN: TX/RX Buffer Selection bit

1 = FIFO is a Transmit FIFO

0 = FIFO is a Receive FIFO

bit 6

TXABAT: Message Aborted bit(2)

1 = Message was aborted

0 = Message completed successfully

bit 5

TXLARB: Message Lost Arbitration bit(3)

1 = Message lost arbitration while being sent

0 = Message did not lose arbitration while being sent

bit 4

TXERR: Error Detected During Transmission bit(3)

1 = A bus error occured while the message was being sent

0 = A bus error did not occur while the message was being sent

bit 3

TXREQ: Message Send Request

TXEN = 1: (FIFO configured as a Transmit FIFO)

Setting this bit to ‘1’ requests sending a message.

The bit will automatically clear when all the messages queued in the FIFO are successfully sent.

Clearing the bit to ‘0’ while set (‘1’) will request a message abort.

TXEN = 0: (FIFO configured as a receive FIFO)

This bit has no effect.

bit 2

RTREN: Auto RTR Enable bit

1 = When a remote transmit is received, TXREQ will be set

0 = When a remote transmit is received, TXREQ will be unaffected

bit 1-0 TXPR<1:0>: Message Transmit Priority bits

11 = Highest message priority

10 = High intermediate message priority

01 = Low intermediate message priority

00 = Lowest message priority

Note 1:

2:

3:

These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits

(C1CON<23:21>) = 100).

This bit is updated when a message completes (or aborts) or when the FIFO is reset.

This bit is reset on any read of this register or when the FIFO is reset.

 2014-2017 Microchip Technology Inc.

DS60001290E-page 267

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