PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 23-18: C1FIFOUAn: CAN FIFO USER ADDRESS REGISTER ‘n’ (‘n’ = 0 THROUGH 15)

Bit

Range

31:24

23:16

15:8

7:0

Bit

31/23/15/7

R-x

R-x

R-x

R-x

Bit

30/22/14/6

R-x

R-x

R-x

R-x

Bit

29/21/13/5

R-x

R-x

R-x

R-x

Bit

Bit

28/20/12/4 27/19/11/3

R-x

R-x

C1FIFOUAn<31:24>

R-x

R-x

C1FIFOUAn<23:16>

R-x

R-x

C1FIFOUAn<15:8>

R-x

R-x

C1FIFOUAn<7:0>

Bit

26/18/10/2

R-x

R-x

R-x

R-x

Bit

25/17/9/1

R-x

R-x

R-x

R-0(1)

Bit

24/16/8/0

R-x

R-x

R-x

R-0(1)

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-0

C1FIFOUAn<31:0>: CAN FIFO User Address bits

TXEN = 1: (FIFO configured as a transmit buffer)

A read of this register will return the address where the next message is to be written (FIFO head).

TXEN = 0: (FIFO configured as a receive buffer)

A read of this register will return the address where the next message is to be read (FIFO tail).

Note 1: This bit will always read ‘0’, which forces byte-alignment of messages.

Note: This register is not guaranteed to read correctly in Configuration mode, and should only be accessed when

the module is not in Configuration mode.

REGISTER 23-19: C1FIFOCIn: CAN MODULE MESSAGE INDEX REGISTER ‘n’ 

(‘n’ = 0 THROUGH 15)

Bit

Range

31:24

23:16

15:8

7:0

Bit

31/23/15/7

U-0

—

U-0

—

U-0

—

U-0

—

Bit

30/22/14/6

U-0

—

U-0

—

U-0

—

U-0

—

Bit

29/21/13/5

U-0

—

U-0

—

U-0

—

U-0

—

Bit

28/20/12/4

U-0

—

U-0

—

U-0

—

R-0

Bit

Bit

Bit

27/19/11/3 26/18/10/2 25/17/9/1

U-0

U-0

U-0

—

—

—

U-0

U-0

U-0

—

—

—

U-0

U-0

U-0

—

—

—

R-0

R-0

R-0

C1FIFOCIn<4:0>

Bit

24/16/8/0

U-0

—

U-0

—

U-0

—

R-0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-5

bit 4-0

Unimplemented: Read as ‘0’

C1FIFOCIn<4:0>: CAN Side FIFO Message Index bits

TXEN = 1: (FIFO configured as a transmit buffer)

A read of this register will return an index to the message that the FIFO will next attempt to transmit.

TXEN = 0: (FIFO configured as a receive buffer)

A read of this register will return an index to the message that the FIFO will use to save the next message.

DS60001290E-page 270

 2014-2017 Microchip Technology Inc.

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