PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 23-17: C1FIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (‘n’ = 0 THROUGH 15)

bit 9

TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)

TXEN = 1: (FIFO configured as a transmit buffer)

1 = FIFO is  half full

0 = FIFO is > half full

TXEN = 0: (FIFO configured as a receive buffer)

Unused, reads ‘0’

bit 8

TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit(1)

TXEN = 1: (FIFO configured as a transmit buffer)

1 = FIFO is empty

0 = FIFO is not empty, at least 1 message queued to be transmitted

TXEN = 0: (FIFO configured as a receive buffer)

Unused, reads ‘0’

bit 7-4 Unimplemented: Read as ‘0’

bit 3 RXOVFLIF: Receive FIFO Overflow Interrupt Flag bit

TXEN = 1: (FIFO configured as a transmit buffer)

Unused, reads ‘0’

TXEN = 0: (FIFO configured as a receive buffer)

1 = Overflow event has occurred

0 = No overflow event occured

bit 2

RXFULLIF: Receive FIFO Full Interrupt Flag bit(1)

TXEN = 1: (FIFO configured as a transmit buffer)

Unused, reads ‘0’

TXEN = 0: (FIFO configured as a receive buffer)

1 = FIFO is full

0 = FIFO is not full

bit 1

RXHALFIF: Receive FIFO Half Full Interrupt Flag bit(1)

TXEN = 1: (FIFO configured as a transmit buffer)

Unused, reads ‘0’

TXEN = 0: (FIFO configured as a receive buffer)

1 = FIFO is half full

0 = FIFO is < half full

bit 0

RXNEMPTYIF: Receive Buffer Not Empty Interrupt Flag bit(1)

TXEN = 1: (FIFO configured as a transmit buffer)

Unused, reads ‘0’

TXEN = 0: (FIFO configured as a receive buffer)

1 = FIFO is not empty, has at least 1 message

0 = FIFO is empty

Note 1: This bit is read-only and reflects the status of the FIFO.

 2014-2017 Microchip Technology Inc.

DS60001290E-page 269

Share Link: