5.1 Interrupts Control Registers
TABLE 5-2: INTERRUPT REGISTER MAP
Bits
31/15 30/14 29/13
28/12
27/11 26/10 25/9 24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000
INTCON
31:16
15:0
—
—
—
—
—
—
—
—
MVEC
—
—
—
—
TPC<2:0>
—
—
—
—
—
—
—
—
—
— 0000
—
INT4EP INT3EP INT2EP INT1EP INT0EP 0000
1010
INTSTAT(4)
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SRIPL<2:0>
—
—
—
—
—
—
—
VEC<5:0>
—
— 0000
0000
31:16
1020 IPTMR
15:0
IPTMR<31:0>
0000
0000
1030
IFS0
31:16 FCEIF RTCCIF FSCMIF
15:0 IC3EIF T3IF INT2IF
AD1IF
OC2IF
OC5IF IC5IF IC5EIF T5IF
IC2IF IC2EIF T2IF INT1IF
INT4IF
OC1IF
OC4IF
IC1IF
IC4IF
IC1EIF
IC4EIF
T1IF
T4IF
INT0IF
INT3IF
CS1IF
OC3IF
CS0IF
IC3IF 0000
CTIF 0000
1040
IFS1
31:16 U3RXIF U3EIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2TXIF SPI2RXIF SPI2EIF PMPEIF PMPIF
15:0 CNDIF CNCIF CNBIF CNAIF I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1TXIF SPI1RXIF SPI1EIF
CNGIF
USBIF(2)
CNFIF CNEIF 0000
CMP2IF CMP1IF 0000
1050
IFS2
31:16 —
—
—
15:0 SPI3RXIF SPI3EIF CANIF
—
CMP3IF
—
—
—
—
—
—
—
—
SPI4TXIF(1) SPI4RXIF(1) SPI4EIF(1) SPI3TXIF 0000
DMA3IF DMA2IF DMA1IF DMA0IF CTMUIF U5TXIF(1) U5RXIF(1) U5EIF(1) U4TXIF U4RXIF U4EIF U3TXIF 0000
1060
IEC0
31:16 FCEIE RTCCIE FSCMIE
15:0 IC3EIE T3IE INT2IE
AD1IE
OC2IE
OC5IE IC5IE IC5EIE T5IE
IC2IE IC2EIE T2IE INT1IE
INT4IE
OC1IE
OC4IE
IC1IE
IC4IE
IC1EIE
IC4EIE
T1IE
T4IE
INT0IE
INT3IE
CS1IE
OC3IE
CS0IE
IC3IE 0000
CTIE 0000
1070
IEC1
31:16 U3RXIE U3EIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2TXIE SPI2RXIE SPI2EIE PMPEIE PMPIE
15:0 CNDIE CNCIE CNBIE CNAIE I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1TXIE SPI1RXIE SPI1EIE
CNGIE CNFIE CNEIE 0000
USBIE(2) CMP2IE CMP1IE 0000
1080
IEC2
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— 0000
—
DMA3IE DMA2IE DMA1IE DMA0IE CTMUIE U5TXIE(1) U5RXIE(1) U5EIE(1) U4TXIE U4RXIE U4EIE U3TXIE 0000
1090
IPC0
31:16
15:0
—
—
—
—
—
—
INT0IP<2:0>
CS0IP<2:0>
INT0IS<1:0>
—
—
—
CS0IS<1:0>
—
—
—
CS1IP<2:0>
CTIP<2:0>
CS1IS<1:0>
CTIS<1:0>
0000
0000
31:16 —
—
—
10A0
IPC1
15:0
—
—
—
INT1IP<2:0>
IC1IP<2:0>
INT1IS<1:0>
—
—
—
IC1IS<1:0>
—
—
—
OC1IP<2:0>
T1IP<2:0>
OC1IS<1:0>
T1IS<1:0>
0000
0000
31:16 —
—
—
10B0
IPC2
15:0
—
—
—
INT2IP<2:0>
IC2IP<2:0>
INT2IS<1:0>
—
—
—
IC2IS<1:0>
—
—
—
OC2IP<2:0>
T2IP<2:0>
OC2IS<1:0>
T2IS<1:0>
0000
0000
10C0
IPC3
31:16
15:0
—
—
—
—
—
—
INT3IP<2:0>
IC3IP<2:0>
INT3IS<1:0>
—
—
—
IC3IS<1:0>
—
—
—
OC3IP<2:0>
T3IP<2:0>
OC3IS<1:0>
T3IS<1:0>
0000
0000
10D0
IPC4
31:16
15:0
—
—
—
—
—
—
INT4IP<2:0>
IC4IP<2:0>
INT4IS<1:0>
—
—
—
IC4IS<1:0>
—
—
—
OC4IP<2:0>
T4IP<2:0>
OC4IS<1:0>
T4IS<1:0>
0000
0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
2:
3:
4:
5:
This bit is only available on 100-pin devices.
This bit is only implemented on devices with a USB module.
With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 “CLR,
SET, and INV Registers” for more information.
This register does not have associated CLR, SET, and INV registers.
This bit is only implemented on devices with a CAN module.