PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

TABLE 5-2: INTERRUPT REGISTER MAP (CONTINUED)

Bits

31/15 30/14 29/13

28/12

27/11 26/10 25/9 24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

31:16 —

—

—

10E0

IPC5

15:0

—

—

—

AD1IP<2:0>

IC5IP<2:0>

AD1IS<1:0>

—

—

—

IC5IS<1:0>

—

—

—

OC5IP<2:0>

T5IP<2:0>

OC5IS<1:0>

T5IS<1:0>

0000

0000

31:16 —

—

—

10F0 IPC6

15:0 —

—

—

CMP1IP<2:0>

RTCCIP<2:0>

CMP1IS<1:0>

—

—

—

RTCCIS<1:0>

—

—

—

FCEIP<2:0>

FSCMIP<2:0>

FCEIS<1:0>

FSCMIS<1:0>

0000

0000

1100

IPC7 31:16

—

—

—

15:0 —

—

—

U1IP<2:0>

USBIP<2:0>(2)

U1IS<1:0>

—

—

—

USBIS<1:0>(2)

—

—

—

SPI1IP<2:0>

CMP2IP<2:0>

SPI1IS<1:0>

CMP2IS<1:0>

0000

0000

1110

IPC8

31:16

15:0

—

—

—

—

—

—

SPI2IP<2:0>

CNIP<2:0>

SPI2IS<1:0>

—

—

—

CNIS<1:0>

—

—

—

PMPIP<2:0>

I2C1IP<2:0>

PMPIS<1:0>

I2C1IS<1:0>

0000

0000

1120

IPC9

31:16

15:0

—

—

—

—

—

—

U4IP<2:0>

I2C2IP<2:0>

U4IS<1:0>

—

—

—

I2C2IS<1:0>

—

—

—

U3IP<2:0>

U2IP<2:0>

U3IS<1:0>

U2IS<1:0>

0000

0000

31:16 —

—

—

1130 IPC10 15:0

—

—

—

DMA1IP<2:0>

CTMUIP<2:0>

DMA1IS<1:0>

—

—

—

CTMUIS<1:0>

—

—

—

DMA0IP<2:0>

U5IP<2:0>

DMA0IS<1:0>

U5IS<1:0>

0000

0000

1140

IPC11

31:16

15:0

—

—

—

—

—

—

CANIP<2:0>(5)

DMA3IP<2:0>

CANIS<1:0>(5)

—

—

—

DMA3IS<1:0>

—

—

—

CMP3IP<2:0>

DMA2IP<2:0>

CMP3IS<1:0>

DMA2IS<1:0>

0000

0000

1150

IPC12

31:16

15:0

—

—

—

—

—

—

—

—

—

—

—

—

SPI4P<2:0>(1)

SPI4S<1:0>(1)

—

—

—

—

—

—

—

—

SPI3P<2:0>

—

—

SPI3S<1:0>

0000

0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

2:

3:

4:

5:

This bit is only available on 100-pin devices.

This bit is only implemented on devices with a USB module.

With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 “CLR,

SET, and INV Registers” for more information.

This register does not have associated CLR, SET, and INV registers.

This bit is only implemented on devices with a CAN module.

Share Link: