DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Inte® Quark SoC X1000—Physical Interfaces

Table 22. Power and Ground Pins (Sheet 2 of 2)

Signal Name

VCC1P0_S0

VCCACLKDDR_1P0

VCCADDR_1P0

VCCADLLDDR_1P0

VCCAPCIE_1P0

VCCAVISA_1P0

VCCPLLDDR_1P0

VNN

OVOUT_1P05_S0

VCCFHVSOC_1P05

VCCFSOC_1P05

VCC1P5_S0

VCCSFRPLLDDR_1P5

OVOUT_1P8_S0

OVOUT_1P8_SLDO

VCC1P8_S0

VCCAA_1P8

VCCAUSB_1P8

VCC3P3_A

VCC3P3_S0

VCCRTC3P3

VSS

VSSA_USB

Nominal

Voltage

1.0V

1.05V

1.5V

1.8V

3.3V

3.3V

0V

Lowest

Active State

Description/Notes

Standard 1.0V Rail for HPLL (Host PLL) and USB Logic

DDR IO Digital Clock Isolated Quiet Supply

DDR IO Digital Supply

DDR IO Digital Isolated Quiet Supply

PCIe Analog Supply

VISA IO Analog Supply

DDR IO Digital PLL High Voltage

Default 1.0V Standard Cell Rail including Core and Uncore Logic

S0 1.05V Rail Standby LDO Output

SoC Fuses Supply

S0

Fuse Digital Sensing

PCIe Band-Gap Supply

DDR IO PLL High Voltage

S0 1.8V Rail Standby LDO Output

S0 1.8V Rail Standby LDO Output (Currently Unused)

S0 1.8V CFIO Supply

1.8V Analog Supply

USB 1.8V Analog Supply

S0 3.3V Rail Standby LDO Input (Currently Unused)

S0 3.3V Rail Standby LDO Input

RTC Well Supply

To be active in G3, the source supply for VCCRTC3P3 must be a 3.0V

G3

coin cell battery or equivalent. If the target application does not

require the RTC to be operational in G3, VCCRTC3P3 should be

supplied from a 3.3V supply that is active in S5.

Ground

-

USB Low-Noise Ground

2.18

Hardware Straps

The pins used for hardware straps are output pins in functional mode.Initially during a

cold boot, these strap pins are configured as inputs. These pins remain inputs until the

external pull up or pull down values are sampled during S0 Power OK. Once sampled,

the pins are enabled as outputs only.

Inte® Quark SoC X1000

DS

56

October 2013

Document Number: 329676-001US

Share Link: