DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Physical Interfaces—Inte® Quark SoC X1000

Table 23.

Hardware Straps

Signal Name

SPI0_MOSI

{SPI0_SCK,

SPI1_MOSI}

LSPI_MOSI

{MAC0_TXDATA[1],

MAC0_TXDATA[0],

MAC1_TXDATA[1]

MAC1_TXDATA[0]

{LSPI_SCK, SD_CLK}

PWR_BTN

Default

1b

11b

1b

000b

0b

00b

0b

Strap Description

Defines Memory Device Width

0b = x16 devices

1b = x8 devices

Defines Memory Device Density

00b = Reserved

01b = 1Gb

10b = 2Gb

11b = 4Gb

Defines the Number of Ranks Enabled

0b = 1 Rank

1b = 2 Ranks

Frequency SKU Power Optimize Mode

[2:1] CPU Clock/DDR Clock

00b = Reserved

01b = 400MHz/800MHz

10b = 200MHz/800MHz

11b = 100MHz/800MHz

[0]

0b = Low Latency

1b = Low Power

Remote Management Unit Firmware Base Address

0b = FFF0_0000h

1b = FFD0_0000h

SDIO Slot Type

00b = Removable Card Slot

01b = Embedded Slot for One Device

10b = Shared Bus Slot

11b = Reserved

Power Button Disable

0b = Power Button Disabled

1b = Power Button Enabled

§§

October 2013

Document Number: 329676-001US

Inte® Quark SoC X1000

DS

57

Share Link: