DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

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Description

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DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

4.2 Data Address Space

The dsPIC33EVXXXGM00X/10X family CPU has a

separate, 16-bit wide data memory space. The Data

Space (DS) is accessed using separate Address Gen-

eration Units (AGUs) for read and write operations. The

data memory maps, which are presented by device

family and memory size, are shown in Figure 4-6 and

Figure 4-8.

All Effective Addresses (EAs) in the data memory space

are 16 bits wide and point to bytes within the DS. This

arrangement gives a Base Data Space address range of

64 Kbytes or 32K words.

The Base Data Space address is used in conjunction

with a Data Space Read or Write Page register

(DSRPAG or DSWPAG) to form an Extended Data

Space (EDS), which has a total address range of

16 Mbytes.

dsPIC33EVXXXGM00X/10X family devices implement

up to 20 Kbytes of data memory (4 Kbytes of data

memory for Special Function Registers and up to

16 Kbytes of data memory for RAM). If an EA points to

a location outside of this area, an all zero word or byte

is returned.

4.2.1 DATA SPACE WIDTH

The data memory space is organized in byte-

addressable, 16-bit wide blocks. Data is aligned in

data memory and registers as 16-bit words, but all DS

EAs resolve to bytes. The Least Significant Bytes

(LSBs) of each word have even addresses, while the

Most Significant Bytes (MSBs) have odd addresses.

4.2.2

DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PIC® MCU

devices and improve Data Space memory usage

efficiency, the dsPIC33EVXXXGM00X/10X family

instruction set supports both word and byte operations.

As a consequence of byte accessibility, all the Effective

Address calculations are internally scaled to step

through word-aligned memory. For example, the core

recognizes that Post-Modified Register Indirect

Addressing mode [Ws++] results in a value of Ws + 1

for byte operations and Ws + 2 for word operations.

A data byte read, reads the complete word that con-

tains the byte, using the LSb of any EA to determine

which byte to select. The selected byte is placed onto

the LSB of the data path. That is, data memory and reg-

isters are organized as two parallel, byte-wide entities

with shared (word) address decode, but separate write

lines. Data byte writes only write to the corresponding

side of the array or register that matches the byte

address.

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, there-

fore, care must be taken when mixing byte and word

operations or translating from 8-bit MCU code. If a

misaligned read or write is attempted, an address error

trap is generated. If the error occurred on a read, the

instruction underway is completed. If the error occurred

on a write, the instruction is executed but the write does

not occur. In either case, a trap is then executed,

allowing the system and/or user application to examine

the machine state prior to execution of the address

Fault.

All byte loads into any W register are loaded into the

LSB; the MSB is not modified.

A Sign-Extend (SE) instruction is provided to allow user

applications to translate 8-bit signed data to 16-bit

signed values. Alternatively, for 16-bit unsigned data,

user applications can clear the MSB of any W register

by executing a Zero-Extend (ZE) instruction on the

appropriate address.

4.2.3 SFR SPACE

The first 4 Kbytes of the Near Data Space, from 0x0000

to 0x0FFF, is primarily occupied by Special Function

Registers (SFRs). These are used by the

dsPIC33EVXXXGM00X/10X family core and peripheral

modules for controlling the operation of the device.

SFRs are distributed among the modules that they

control and are generally grouped together by module.

Much of the SFR space contains unused addresses;

these are read as ‘0’.

Note:

The actual set of peripheral features and

interrupts varies by the device. Refer to the

corresponding device tables and pinout

diagrams for device-specific information.

4.2.4 NEAR DATA SPACE

The 8-Kbyte area, between 0x0000 and 0x1FFF, is

referred to as the Near Data Space. Locations in this

space are directly addressable through a 13-bit abso-

lute address field within all memory direct instructions.

Additionally, the whole DS is addressable using MOV

instructions, which support Memory Direct Addressing

mode with a 16-bit address field, or by using Indirect

Addressing mode using a Working register as an

Address Pointer.

DS70005144E-page 36

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