DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

3.0 CPU

Note 1: This data sheet summarizes the features

of the dsPIC33EVXXXGM00X/10X family

of devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to “CPU” (DS70359) in the

“dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

The CPU has a 16-bit (data) modified Harvard archi-

tecture with an enhanced instruction set, including

significant support for digital signal processing. The

CPU has a 24-bit instruction word with a variable length

opcode field. The Program Counter (PC) is 23 bits wide

and addresses up to 4M x 24 bits of user program

memory space.

An instruction prefetch mechanism helps maintain

throughput and provides predictable execution. Most

instructions execute in a single-cycle effective execu-

tion rate, with the exception of instructions that change

the program flow, the double-word move (MOV.D)

instruction, PSV accesses and the table instructions.

Overhead-free program loop constructs are supported

using the DO and REPEAT instructions, both of which

are interruptible at any point.

3.1 Registers

The dsPIC33EVXXXGM00X/10X family devices have

sixteen, 16-bit Working registers in the programmer’s

model. Each of the Working registers can act as a

Data, Address or Address Offset register. The sixteenth

Working register (W15) operates as a Software Stack

Pointer for interrupts and calls.

In addition, the dsPIC33EVXXXGM00X/10X devices

include two alternate Working register sets, which

consist of W0 through W14. The alternate registers can

be made persistent to help reduce the saving and

restoring of register content during Interrupt Service

Routines (ISRs). The alternate Working registers can

be assigned to a specific Interrupt Priority Level (IPL1

through IPL6) by configuring the CTXTx<2:0> bits in

the FALTREG Configuration register.

The alternate Working registers can also be accessed

manually by using the CTXTSWP instruction.

The CCTXI<2:0> and MCTXI<2:0> bits in the CTXTSTAT

register can be used to identify the current, and most

recent, manually selected Working register sets.

3.2 Instruction Set

The device instruction set has two classes of instruc-

tions: the MCU class of instructions and the DSP class

of instructions. These two instruction classes are

seamlessly integrated into the architecture and exe-

cute from a single execution unit. The instruction set

includes many addressing modes and was designed

for optimum C compiler efficiency.

3.3 Data Space Addressing

The Base Data Space can be addressed as 4K words

or 8 Kbytes and is split into two blocks, referred to as X

and Y data memory. Each memory block has its own

independent Address Generation Unit (AGU). The

MCU class of instructions operates solely through the

X memory AGU, which accesses the entire memory

map as one linear Data Space. On dsPIC33EV

devices, certain DSP instructions operate through the

X and Y AGUs to support dual operand reads, which

splits the data address space into two parts. The X and

Y Data Space boundary is device-specific.

The upper 32 Kbytes of the Data Space (DS) memory

map can optionally be mapped into Program Space (PS)

at any 16K program word boundary. The Program-to-

Data Space mapping feature, known as Program Space

Visibility (PSV), lets any instruction access Program

Space as if it were Data Space. Moreover, the Base Data

Space address is used in conjunction with a Data Space

Read or Write Page register (DSRPAG or DSWPAG) to

form an Extended Data Space (EDS) address. The EDS

can be addressed as 8M words or 16 Mbytes. For more

information on EDS, PSV and table accesses, refer to

“Data Memory” (DS70595) and “dsPIC33E/PIC24E

Program Memory” (DS70000613) in the “dsPIC33/

PIC24 Family Reference Manual”.

On dsPIC33EV devices, overhead-free circular buffers

(Modulo Addressing) are supported in both X and Y

address spaces. The Modulo Addressing removes the

software boundary checking overhead for DSP

algorithms. The X AGU Circular Addressing can be

used with any of the MCU class of instructions. The X

AGU also supports Bit-Reversed Addressing to greatly

simplify input or output data reordering for radix-2 FFT

algorithms. Figure 3-1 illustrates the block diagram of

the dsPIC33EVXXXGM00X/10X family devices.

3.4 Addressing Modes

The CPU supports these addressing modes:

• Inherent (no operand)

• Relative

• Literal

• Memory Direct

• Register Direct

• Register Indirect

Each instruction is associated with a predefined

addressing mode group, depending upon its functional

requirements. As many as six addressing modes are

supported for each instruction.

 2013-2016 Microchip Technology Inc.

DS70005144E-page 21

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