DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED)

bit 7-5

bit 4

bit 3

bit 2

bit 1

bit 0

IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2)

111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled

110 = CPU Interrupt Priority Level is 6 (14)

101 = CPU Interrupt Priority Level is 5 (13)

100 = CPU Interrupt Priority Level is 4 (12)

011 = CPU Interrupt Priority Level is 3 (11)

010 = CPU Interrupt Priority Level is 2 (10)

001 = CPU Interrupt Priority Level is 1 (9)

000 = CPU Interrupt Priority Level is 0 (8)

RA: REPEAT Loop Active bit

1 = REPEAT loop is in progress

0 = REPEAT loop is not in progress

N: MCU ALU Negative bit

1 = Result was negative

0 = Result was non-negative (zero or positive)

OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude that

causes the sign bit to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)

0 = Overflow has not occurred for signed arithmetic

Z: MCU ALU Zero bit

1 = An operation that affects the Z bit has set it at some time in the past

0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)

C: MCU ALU Carry/Borrow bit

1 = A carry-out from the Most Significant bit (MSb) of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1:

2:

3:

The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL3 = 1. User interrupts are disabled when IPL3 = 1.

The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.

A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by

clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not

be modified using the bit operations.

DS70005144E-page 26

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