DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

REGISTER 3-2: CORCON: CORE CONTROL REGISTER

R/W-0

VAR

bit 15

U-0

R/W-0

R/W-0

R/W-0

R-0

—

US1

US0

EDT(1)

DL2

R-0

R-0

DL1

DL0

bit 8

R/W-0

R/W-0

R/W-1

R/W-0

R/C-0

R-0

SATA

SATB

SATDW

ACCSAT

IPL3(2)

SFA

bit 7

R/W-0

RND

R/W-0

IF

bit 0

Legend:

R = Readable bit

-n = Value at POR

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

bit 14

bit 13-12

bit 11

bit 10-8

bit 7

bit 6

bit 5

bit 4

VAR: Variable Exception Processing Latency Control bit

1 = Variable exception processing latency is enabled

0 = Fixed exception processing latency is enabled

Unimplemented: Read as ‘0’

US<1:0>: DSP Multiply Unsigned/Signed Control bits

11 = Reserved

10 = DSP engine multiplies are mixed-sign

01 = DSP engine multiplies are unsigned

00 = DSP engine multiplies are signed

EDT: Early DO Loop Termination Control bit(1)

1 = Terminates executing the DO loop at the end of the current loop iteration

0 = No effect

DL<2:0>: DO Loop Nesting Level Status bits

111 = 7 DO loops are active

•

•

•

001 = 1 DO loop is active

000 = 0 DO loops are active

SATA: ACCA Saturation Enable bit

1 = Accumulator A saturation is enabled

0 = Accumulator A saturation is disabled

SATB: ACCB Saturation Enable bit

1 = Accumulator B saturation is enabled

0 = Accumulator B saturation is disabled

SATDW: Data Space Write from DSP Engine Saturation Enable bit

1 = Data Space write saturation is enabled

0 = Data Space write saturation is disabled

ACCSAT: Accumulator Saturation Mode Select bit

1 = 9.31 saturation (super saturation)

0 = 1.31 saturation (normal saturation)

Note 1: This bit is always read as ‘0’.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

 2013-2016 Microchip Technology Inc.

DS70005144E-page 27

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