DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC33EV64GM102-I/SO
Microchip Technology
DSPIC33EV64GM102-I/SO Datasheet PDF : 500 Pages
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dsPIC33EVXXXGM00X/10X FAMILY
3.6 CPU Control Registers
REGISTER 3-1: SR: CPU STATUS REGISTER
R/W-0
OA
bit 15
R/W-0
OB
R/W-0
SA(3)
R/W-0
SB(3)
R/C-0
OAB
R/C-0
SAB
R-0
R/W-0
DA
DC
bit 8
R/W-0
R/W-0
R/W-0
R-0
IPL2(1,2)
IPL1(1,2)
IPL0(1,2)
RA
bit 7
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
OA: Accumulator A Overflow Status bit
1 = Accumulator A has overflowed
0 = Accumulator A has not overflowed
OB: Accumulator B Overflow Status bit
1 = Accumulator B has overflowed
0 = Accumulator B has not overflowed
SA: Accumulator A Saturation ‘Sticky’ Status bit(3)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
SB: Accumulator B Saturation ‘Sticky’ Status bit(3)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulator A or B has overflowed
0 = Accumulator A and B have not overflowed
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
1 = Accumulator A or B is saturated or has been saturated at some time
0 = Accumulator A and B have not been saturated
DA: DO Loop Active bit
1 = DO loop is in progress
0 = DO loop is not in progress
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1:
2:
3:
The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL3 = 1. User interrupts are disabled when IPL3 = 1.
The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.
A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using the bit operations.
2013-2016 Microchip Technology Inc.
DS70005144E-page 25
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