DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

3.7 Arithmetic Logic Unit (ALU)

The dsPIC33EVXXXGM00X/10X family ALU is 16 bits

wide and is capable of addition, subtraction, bit shifts

and logic operations. Unless otherwise mentioned,

arithmetic operations are two’s complement in nature.

Depending on the operation, the ALU can affect the

values of the Carry (C), Zero (Z), Negative (N),

Overflow (OV) and Digit Carry (DC) Status bits in the

SR register. The C and DC Status bits operate as

Borrow and Digit Borrow bits, respectively, for

subtraction operations.

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

The data for the ALU operation can come from the W

register array or from the data memory, depending on

the addressing mode of the instruction. Similarly, the

output data from the ALU can be written to the W

register array or a data memory location.

For information on the SR bits affected by each

instruction, refer to the “16-bit MCU and DSC

Programmer’s Reference Manual” (DS70157).

The core CPU incorporates hardware support for both

multiplication and division. This includes a dedicated

hardware multiplier and support hardware for 16-bit

divisor division.

3.7.1 MULTIPLIER

Using the high-speed, 17-bit x 17-bit multiplier, the ALU

supports unsigned, signed or mixed-sign operation in

several MCU multiplication modes:

• 16-bit x 16-bit signed

• 16-bit x 16-bit unsigned

• 16-bit signed x 5-bit (literal) unsigned

• 16-bit signed x 16-bit unsigned

• 16-bit unsigned x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit signed

• 8-bit unsigned x 8-bit unsigned

3.7.2 DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and unsigned integer divide operations with the

following data sizes:

• 32-bit signed/16-bit signed divide

• 32-bit unsigned/16-bit unsigned divide

• 16-bit signed/16-bit signed divide

• 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0

and the remainder in W1. The 16-bit signed and

unsigned DIV instructions can specify any W register

for both the 16-bit divisor (Wn) and any W register

(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.

The divide algorithm takes the single-cycle per bit of

the divisor, so both 32-bit/16-bit and 16-bit/16-bit

instructions take the same number of cycles to

execute.

3.8 DSP Engine

The DSP engine consists of a high-speed, 17-bit x 17-bit

multiplier, a 40-bit barrel shifter and a 40-bit adder/

subtracter (with two target accumulators, round and

saturation logic).

The DSP engine can also perform inherent accumulator-

to-accumulator operations that require no additional

data. These instructions are ADD, SUB and NEG.

The DSP engine has options selected through bits in

the CPU Core Control register (CORCON) as follows:

• Fractional or Integer DSP Multiply (IF)

• Signed, Unsigned or Mixed-Sign DSP Multiply (US)

• Conventional or Convergent Rounding (RND)

• Automatic Saturation On/Off for ACCA (SATA)

• Automatic Saturation On/Off for ACCB (SATB)

• Automatic Saturation On/Off for Writes to Data

Memory (SATDW)

• Accumulator Saturation mode Selection

(ACCSAT)

TABLE 3-2:

Instruction

CLR

ED

EDAC

MAC

MAC

MOVSAC

MPY

MPY

MPY.N

MSC

DSP INSTRUCTIONS

SUMMARY

Algebraic

Operation

ACC Write

Back

A=0

Yes

A = (x – y)2

No

A = A + (x – y)2

No

A = A + (x • y)

Yes

A = A + x2

No

No change in A

Yes

A=x•y

No

A = x2

No

A=–x•y

No

A=A–x•y

Yes

DS70005144E-page 30

 2013-2016 Microchip Technology Inc.

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