dsPIC33EVXXXGM00X/10X FAMILY
REGISTER 3-3:
U-0
—
bit 15
CTXTSTAT: CPU W REGISTER CONTEXT STATUS REGISTER
U-0
U-0
U-0
U-0
R-0
R-0
—
—
—
—
CCTXI2
CCTXI1
U-0
—
bit 7
U-0
U-0
U-0
U-0
R-0
R/W-0
—
—
—
—
MCTXI2
MCTXI1
R-0
CCTXI0
bit 8
R/W-0
MCTXI0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
bit 10-8
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
CCTXI<2:0>: Current (W Register) Context Identifier bits
111 = Reserved
•
•
•
011 = Reserved
010 = Alternate Working Register Set 2 is currently in use
001 = Alternate Working Register Set 1 is currently in use
000 = Default register set is currently in use
Unimplemented: Read as ‘0’
MCTXI<2:0>: Manual (W Register) Context Identifier bits
111 = Reserved
•
•
•
011 = Reserved
010 = Alternate Working Register Set 2 was most recently manually selected
001 = Alternate Working Register Set 1 was most recently manually selected
000 = Default register set was most recently manually selected
2013-2016 Microchip Technology Inc.
DS70005144E-page 29