DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

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Description

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DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

4.2.5 X AND Y DATA SPACES

The dsPIC33EVXXXGM00X/10X family core has two

Data Spaces: X and Y. These Data Spaces can be

considered either separate (for some DSP instructions)

or as one unified, linear address range (for MCU

instructions). The Data Spaces are accessed using two

Address Generation Units (AGUs) and separate data

paths. This feature allows certain instructions to

concurrently fetch two words from RAM, thereby

enabling efficient execution of DSP algorithms, such as

Finite Impulse Response (FIR) filtering and Fast

Fourier Transform (FFT).

The X DS is used by all instructions and supports all

addressing modes. The X DS has separate read and

write data buses. The X read data bus is the read data

path for all instructions that view the DS as combined X

and Y address space. It is also the X data prefetch path

for the dual operand DSP instructions (MAC class).

The Y DS is used in concert with the X DS by the MAC

class of instructions (CLR, ED, EDAC, MAC, MOVSAC,

MPY, MPY.N and MSC) to provide two concurrent data

read paths.

Both the X and Y Data Spaces support Modulo

Addressing mode for all instructions, subject to

addressing mode restrictions. Bit-Reversed Addressing

mode is only supported for writes to the X Data Space.

All data memory writes, including in DSP instructions,

view Data Space as combined X and Y address space.

The boundary between the X and Y Data Spaces is

device-dependent and is not user-programmable.

DS70005144E-page 40

 2013-2016 Microchip Technology Inc.

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