ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF518KSWZ-ENG

Blackfin Embedded Processor

Analog Devices 

ADSP-BF512/BF514/BF516/BF518 (F)

Parallel Peripheral Interface Timing

Table 24 and Figure 12 on Page 32, Figure 18 on Page 38, and

Figure 19 on Page 39 describe parallel peripheral interface

operations.

Table 24. Parallel Peripheral Interface Timing

Parameter

Timing Requirements

tPCLKW

tPCLK

PPI_CLK Width1

PPI_CLK Period1

Timing Requirements - GP Input and Frame Capture Modes

tSFSPE

External Frame Sync Setup Before PPI_CLK

(Nonsampling Edge for Rx, Sampling Edge for Tx)

tHFSPE

External Frame Sync Hold After PPI_CLK

tSDRPE

Receive Data Setup Before PPI_CLK

tHDRPE

Receive Data Hold After PPI_CLK

Switching Characteristics - GP Output and Frame Capture Modes

tDFSPE

tHOFSPE

tDDTPE

tHDTPE

Internal Frame Sync Delay After PPI_CLK

Internal Frame Sync Hold After PPI_CLK

Transmit Data Delay After PPI_CLK

Transmit Data Hold After PPI_CLK

1 PPI_CLK frequency cannot exceed fSCLK/2

Preliminary Technical Data

Min

Max

Unit

6.4

ns

16.0

ns

6.7

ns

1.0

ns

3.5

ns

1.5

ns

8.8

ns

1.7

ns

9.0

ns

1.8

ns

PPI_CLK

POLC = 0

PPI_CLK

POLC = 1

POLS = 1

PPI_FS1

POLS = 0

POLS = 1

PPI_FS2

POLS = 0

PPI_DATA

DATA0 IS

SAMPLED

DATA1 IS

SAMPLED

tSFSPE

tHFSPE

tSDRPE

tHDRPE

Figure 12. PPI GP Rx Mode with External Frame Sync Timing

Rev. PrE | Page 32 of 62 | March 2009

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