ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF518KSWZ-ENG

Blackfin Embedded Processor

Analog Devices 

ADSP-BF512/BF514/BF516/BF518 (F)

Serial Peripheral Interface (SPI) Port—Master Timing

Table 31 and Figure 20 describe SPI port master operations.

Table 31. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter

Timing Requirements

tSSPIDM

Data Input Valid to SCK Edge (Data Input Setup)

tHSPIDM

SCK Sampling Edge to Data Input Invalid

Switching Characteristics

tSDSCIM

tSPICHM

tSPICLM

tSPICLK

tHDSM

tSPITDM

tDDSPIDM

tHDSPIDM

SPISELx low to First SCK Edge

Serial Clock High Period

Serial Clock Low Period

Serial Clock Period

Last SCK Edge to SPISELx High

Sequential Transfer Delay

SCK Edge to Data Out Valid (Data Out Delay)

SCK Edge to Data Out Invalid (Data Out Hold)

Preliminary Technical Data

Min

Max

11.6

–1.5

2 × tSCLK –1.5

2 × tSCLK –1.5

2 × tSCLK –1.5

4 × tSCLK

2 × tSCLK –1.5

2 × tSCLK

0

6

–1.0

4.0

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

SPIxSELy

(OUTPUT)

SCKx

(CPOL = 0)

(OUTPUT)

SCKx

(CPOL = 1)

(OUTPUT)

tSDSCIM

tSPICHM

tSPICLM

tSPICLM

tSPICHM

tSPICLK

tHDSPIDM

tDDSPIDM

tHDSM

tSPITD M

MOSIx

(OUTPUT)

CPHA=1

MISOx

(INPUT)

MSB

MSB

VALID

LSB

tSSPIDM

LSB

VALID

tHSPIDM

tHDSPIDM

tDDSPIDM

MOSIx

(OUTPUT)

MSB

LSB

CPHA=0

MISOx

(INPUT)

tSSPIDM

tHSPIDM

MSB

VALID

LSB

VALID

Figure 20. Serial Peripheral Interface (SPI) Port—Master Timing

Rev. PrE | Page 40 of 62 | March 2009

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