ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF518KSWZ-ENG

Blackfin Embedded Processor

Analog Devices 

Preliminary Technical Data

ADSP-BF512/BF514/BF516/BF518 (F)

SD/SDIO Controller Timing

Table 25 and Figure 16 describe SD/SDIO Controller Timing.

Table 26 and Figure 17 describe SD/SDIO controller (high

speed) timing.

Table 25. SD/SDIO Controller Timing

Parameter

Min

Timing Requirements

tISU Input Setup Time

7.2

tIH

Input Hold Time

2

Switching Characteristics

fPP Clock Frequency Data Transfer Mode

fOD Clock Frequency Identification Mode

tWL Clock Low Time

tWH Clock High Time

tTLH Clock Rise Time

tTHL Clock Fall Time

tODLY Output Delay Time During Data Transfer Mode

tODLY Output Delay Time During Identification Mode

0

01/100

15

15

–1

–1

1 0 kHz means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.

Max

20

400

10

10

14

50

Unit

ns

ns

MHz

kHz

ns

ns

ns

ns

ns

ns

VOH

(MIN)

VOL

(MAX)

SD_CLK

INPUT1

tPP

tWL

tWH

tTHL

tTLH

tISU

tIH

OUTPUT2

1 Input includes SD_Dx and SD_CMD

2 Output includes SD_Dx and SD_CMD

tODLY(MAX)

Figure 16. SD/SDIO Controller Timing

tODLY(MIN)

Rev. PrE | Page 35 of 62 | March 2009

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