ADSP-BF512/BF514/BF516/BF518 (F)
Table 26. SD/SDIO Controller Timing (High Speed Mode)
Parameter
Timing Requirements
tISU
Input Setup Time
tIH
Input Hold Time
Switching Characteristics
fPP
Clock Frequency Data Transfer Mode
tWL
Clock Low Time
tWH
Clock High Time
tTLH
Clock Rise Time
tTHL
Clock Fall Time
tODLY Output Delay Time During Data Transfer Mode
tOH
Output Hold Time
Preliminary Technical Data
Min
Max Unit
7.2
ns
2
ns
0
40 MHz
9.5
ns
9.5
ns
3 ns
3 ns
2 ns
2.5
ns
SD_CLK
INPUT 1
tTHL
1.5 V
tPP
tWL
tWH
tISU
tTLH
tIH
OUTPUT 2
1 Input includes SD_Dx and SD_CMD
tODLY
tOH
2 Output includes SD_Dx and SD_CMD
Figure 17. SD/SDIO Controller Timing (High-Speed Mode)
Rev. PrE | Page 36 of 62 | March 2009