ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF518KSWZ-ENG

Blackfin Embedded Processor

Analog Devices 

ADSP-BF512/BF514/BF516/BF518 (F)

Preliminary Technical Data

Table 30. External Late Frame Sync

Parameter

Min

Switching Characteristics

tDDTLFSE

tDTENLFSE

Data Delay from Late External TFSx or External RFSx with MCE = 1, MFD = 01, 2

Data Enable from Late FS or MCE = 1, MFD = 01, 2

0.0

1 MCE = 1, TFSx enable and TFSx valid follow tDDTENFS and tDDTLFSE.

2 If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2 then tDDTTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFS apply.

Max

Unit

10.0

ns

ns

DATA RECEIVE—INTERNAL CLOCK

DRIVE

EDGE

tSCLKIW

RSCLKx

tHOFSI

tDFSI

tSFSI

RFSx

SAMPLE

EDGE

tHFSI

DATA RECEIVE—EXTERNAL CLOCK

DRIVE

EDGE

tSCLKEW

SAMPLE

EDGE

RSCLKx

tHOFSE

tDFSE

tSFSE

RFSx

DRx

tSDRI

tHDR I

DRx

tSDRE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT—INTERNAL CLOCK

DRIVE

EDGE

tSCLKIW

SAMPLE

EDGE

TSCLKx

tHOFSI

tDFSI

tSFSI

TFSx

tHDTI

tDDTI

DTx

tHFSI

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE

EDGE

tSCLKEW

SAMPLE

EDGE

TSCLKx

tHOFSE

tDFSE

tSFSE

TFSx

tHDTE

tDDTE

DTx

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.

Figure 18. Serial Ports

tHFSE

tHDRE

tHFSE

Rev. PrE | Page 38 of 62 | March 2009

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